View CAT93C76BHU4I-GT3_9019295.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2013 may, 2018 ? rev.1 1 publication order number: cat93c76b/d cat93c76b eeprom serial 8-kb microwire description the cat93c76b is an 8 ? kb microwire serial eeprom memory device which is configured as either registers of 16 bits (org pin at v cc or not connected) or 8 bits (org pin at gnd). each register can be written (or read) serially by using the di (or do) pin. the cat93c76b is manufactured using on semiconductor?s advanced cmos eeprom floating gate technology. the device is designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years. the device is available in 8 ? pin pdip, soic, tssop, msop and 8 ? pad udfn packages. features ? high speed operation: 4 mhz (5 v), 2 mhz (1.8 v) ? 1.8 v (1.65 v*) to 5.5 v supply voltage range ? selectable x8 or x16 memory organization ? self ? timed write cycle with auto ? clear ? software write protection ? power ? up inadvertant write protection ? low power cmos technology ? 1,000,000 program/erase cycles ? 100 year data retention ? industrial and extended temperature ranges ? sequential read ? 8 ? pin pdip, soic, tssop, msop and 8 ? pad udfn packages ? this device is pb ? free, halogen free/bfr free and rohs compliant ? cs sk org do di gnd v cc figure 1. functional symbol cat93c76b *cat93c76bxx ? xxl (t a = ? 20 c to +85 c) ?for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. www. onsemi.com see detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. ordering information pin configuration gnd nc v cc do di sk cs 1 soic ? 8 v suffix case 751bd org pdip (l), soic (v), tssop (y), udfn (hu4), msop (z) (top view) pdip ? 8 l suffix case 646aa tssop ? 8 y suffix case 948al chip select cs serial clock input sk serial data input di serial data output do power supply v cc ground gnd function pin name pin function memory organization org no connection nc udfn ? 8 hu4 suffix case 517az note: when the org pin is connected to v cc , the x16 organization is selected. when it is connected to ground, the x8 organization is selected. if the org pin is left unconnected, then an internal pull ? up device will select the x16 organization. msop ? 8 z suffix case 846ad
cat93c76b www. onsemi.com 2 table 1. absolute maximum ratings parameters ratings units temperature under bias ? 55 to +125 c storage temperature ? 65 to +150 c voltage on any pin with respect to ground (note 1) ? 2.0 to +v cc +2.0 v v cc with respect to ground ? 2.0 to +7.0 v lead soldering temperature (10 seconds) 300 c output short circuit current (note 2) 100 ma stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. the minimum dc input voltage is ? 0.5 v. during transitions, inputs may undershoot to ? 2.0 v for periods of less than 20 ns. maximum dc voltage on output pins is v cc +0.5 v, which may overshoot to v cc +2.0 v for periods of less than 20 ns. 2. output shorted for no more than one second. table 2. reliability characteristics (note 2) symbol parameter reference test method min units n end (note 3) endurance mil ? std ? 883, test method 1033 1,000,000 cycles / byte t dr (note 3) data retention mil ? std ? 883, test method 1008 100 years v zap (note 3) esd susceptibility mil ? std ? 883, test method 3015 2,000 v i lth (notes 3, 4) latch ? up jedec standard 17 100 ma 3. these parameters are tested initially and after a design or process change that affects the parameter. 4. latch ? up protection is provided for stresses up to 100 ma on i/o pins from ? 1 v to v cc + 1 v. table 3. d.c. operating characteristics (v cc = +1.8 v to +5.5 v, t a = ? 40 c to +125 c, v cc = +1.65 v to +5.5 v, t a = ? 20 c to +85 c unless otherwise specified.) symbol parameter test conditions min max units i cc1 supply current (write) write, v cc = 5.0 v 2 ma i cc2 supply current (read) read, do open, f sk = 2 mhz, v cc = 5.0 v 500 a i sb1 standby current (x8 mode) v in = gnd or v cc cs = gnd, org = gnd t a = ? 40 c to +85 c 2 a t a = ? 40 c to +125 c 5 i sb2 standby current (x16 mode) v in = gnd or v cc cs = gnd, org = float or v cc t a = ? 40 c to +85 c 1 a t a = ? 40 c to +125 c 3 i li input leakage current v in = gnd to v cc t a = ? 40 c to +85 c 1 a t a = ? 40 c to +125 c 2 i lo output leakage current v out = gnd to v cc cs = gnd t a = ? 40 c to +85 c 1 a t a = ? 40 c to +125 c 2 v il1 input low voltage 4.5 v v cc < 5.5 v ? 0.1 0.8 v v ih1 input high voltage 4.5 v v cc < 5.5 v 2 v cc + 1 v v il2 input low voltage 1.65 v v cc < 4.5 v 0 v cc x 0.2 v v ih2 input high voltage 1.65 v v cc < 4.5 v v cc x 0.7 v cc + 1 v v ol1 output low voltage 4.5 v v cc < 5.5 v, i ol = 3 ma 0.4 v v oh1 output high voltage 4.5 v v cc < 5.5 v, i oh = ? 400 a 2.4 v v ol2 output low voltage 1.65 v v cc < 4.5 v, i ol = 1 ma 0.2 v v oh2 output high voltage 1.65 v v cc < 4.5 v, i oh = ? 100 a v cc ? 0.2 v table 4. pin capacitance (note 3) symbol test conditions min typ max units c out output capacitance (do) v out = 0 v 5 pf c in input capacitance (cs, sk, di, org) v in = 0 v 5 pf
cat93c76b www. onsemi.com 3 table 5. instruction set (note 5) instruction start bit opcode address data comments x8 x16 x8 x16 read 1 10 a10 ? a0 a9 ? a0 read address an? a0 erase 1 11 a10 ? a0 a9 ? a0 clear address an? a0 write 1 01 a10 ? a0 a9 ? a0 d7 ? d0 d15 ? d0 write address an? a0 ewen 1 00 11xxxxxxxxx 11xxxxxxxx write enable ewds 1 00 00xxxxxxxxx 00xxxxxxxx write disable eral* 1 00 10xxxxxxxxx 10xxxxxxxx clear all addresses wral* 1 00 01xxxxxxxxx 01xxxxxxxx d7 ? d0 d15 ? d0 write all addresses * not available at v cc < 1.8 v 5. address bit a10 for the 1,024x8 org. and a9 for the 512x16 org. are ?don?t care? bits, but must be kept at either a ?1? or ?0? for read , write and erase commands. table 6. a.c. characteristics (v cc = +1.8 v to +5.5 v, t a = ? 40 c to +125 c, v cc = +1.65 v to +5.5 v, t a = ? 20 c to +85 c unless otherwise specified.) symbol parameter v cc < 4.5 v v cc > 4.5 v units min max min max t css cs setup time 50 50 ns t csh cs hold time 0 0 ns t dis di setup time 100 50 ns t dih di hold time 100 50 ns t pd1 output delay to 1 0.25 0.1 s t pd0 output delay to 0 0.25 0.1 s t hz (note 6) output delay to high ? z 100 100 ns t ew program/erase pulse width 5 5 ms t csmin minimum cs low time 0.25 0.1 s t skhi minimum sk high time 0.25 0.1 s t sklow minimum sk low time 0.25 0.1 s t sv output delay to status valid 0.25 0.1 s sk max maximum clock frequency dc 2000 dc 4000 khz 6. this parameter is tested initially and after a design or process change that affects the parameter. table 7. power ? up timing (notes 6, 7) symbol parameter max units t pur power ? up to read operation 1 ms t puw power ? up to write operation 1 ms 7. t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. table 8. a.c. test conditions input rise and fall times 50 ns input pulse voltages 0.4 v to 2.4 v 4.5 v v cc 5.5 v timing reference voltages 0.8 v, 2.0 v 4.5 v v cc 5.5 v input pulse voltages 0.2 v cc to 0.7 v cc 1.65 v v cc 4.5 v timing reference voltages 0.5 v cc 1.65 v v cc 4.5 v output load current source i olmax /i ohmax ; cl = 100 pf
cat93c76b www. onsemi.com 4 device operation the cat93c76b is a 8192 ? bit nonvolatile memory intended for use with industry standard microprocessors. the cat93c76b can be organized as either registers of 16 bits or 8 bits. when organized as x16, seven 13 ? bit instructions control the read, write and erase operations of the device. when organized as x8, seven 14 ? bit instructions control the read, write and erase operations of the device. the cat93c76b operates on a single power supply and will generate on chip, the high voltage required during any write operation. instructions, addresses, and write data are clocked into the di pin on the rising edge of the clock (sk). the do pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. the ready/busy status can be determined after the start of a write operation by selecting the device (cs high) and polling the do pin; do low indicates that the write operation is not completed, while do high indicates that the device is ready for the next instruction. if necessary, the do pin may be placed back into a high impedance state during chip select by shifting a dummy ?1? into the di pin. the do pin will enter the high impedance state on the falling edge of the clock (sk). placing the do pin into the high impedance state is recommended in applications where the di pin and the do pin are to be tied together to form a common di/o pin. the format for all instructions sent to the device is a logical ?1? start bit, a 2 ? bit (or 4 ? bit) opcode, 10 ? bit address (an additional bit when organized x8) and for write operations a 16 ? bit data field (8 ? bit for x8 organizations). the most significant bit of the address is ?don?t care? but it must be present. read upon receiving a read command and an address (clocked into the di pin), the do pin of the ca t93c76b will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (msb first). the output data bits will toggle on the rising edge of the sk clock and are stable after the specified time delay (t pd0 or t pd1 ). for the cat93c76b, after the initial data word has been shifted out and cs remains asserted with the sk clock continuing to toggle, the device will automatically increment to the next address and shift out the next data word in a sequential read mode. as long as cs is continuously asserted and sk continues to toggle, the device will keep incrementing to the next address automatically until it reaches the end of the address space, then loops back to address 0. in the sequential read mode, only the initial data word is preceeded by a dummy zero bit. all subsequent data words will follow without a dummy zero bit. write after receiving a write command, address and the data, the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clocking clear and data store cycle of the memory location specified in the instruction. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat93c76b can be determined by selecting the device and polling the do pin. since this device features auto ? clear before write, it is not necessary to erase a memory location before it is written into. sk di cs do valid valid data valid figure 2. synchronous data timing t css t skhi t sklow t dis t dis t dih t csh t csmn t pd0 , t pd1
cat93c76b www. onsemi.com 5 sk cs di do high ? z 11 0 dummy 0 address + 1 address + 2 address + n don?t care figure 3. read instruction timing a n a n ? 1 a 0 d 15 . . . or d 7 . . . d 15 . . . d 0 or d 7 . . . d 0 d 15 . . . d 0 or d 7 . . . d 0 d 15 . . . d 0 or d 7 . . . d 0 sk cs di do standby high ? z high ? z 101 busy ready status verify figure 4. write instruction timing a n a n ? 1 a 0 d n d 0 t csmin t hz t sv t ew
cat93c76b www. onsemi.com 6 erase upon receiving an erase command and address, the cs (chip select) pin must be deasserted for a minimum of t csmin . the falling edge of cs will start the self clocking clear cycle of the selected memory location. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat93c76b can be determined by selecting the device and polling the do pin. once cleared, the content of a cleared location returns to a logical ?1? state. erase/write enable and disable the cat93c76b powers up in the write disable state. any writing after power ? up or after an ewds (write disable) instruction must first be preceded by the ewen (write enable) instruction. once the write instruction is enabled, it will remain enabled until power to the device is removed, or the ewds instruction is sent. the ewds instruction can be used to disable all cat93c76b write and clear instructions, and will prevent any accidental writing or clearing of the device. data can be read normally from the device regardless of the write enable/disable status. erase all upon receiving an eral command, the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clocking clear cycle of all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat93c76b can be determined by selecting the device and polling the do pin. once cleared, the contents of all memory bits return to a logical ?1? state. write all upon receiving a wral command and data, the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clocking data write to all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat93c76b can be determined by selecting the device and polling the do pin. it is not necessary for all memory locations to be cleared before the wral command is executed. note 1: after the last data bit has been sampled, chip select (cs) must be brought low before the next rising edge of the clock (sk) in order to start the self ? timed high voltage cycle. this is important because if cs is brought low before or after this specific frame window, the addressed location will not be programmed or erased. power ? on reset (por) the cat93c76b incorporates power ? on reset (por) circuitry which protects the device against malfunctioning while v cc is lower than the recommended operating voltage. the device will power up into a read ? only state and will power ? down into a reset state when v cc crosses the por level of ~1.3 v. sk cs di do standby high ? z high ? z 1 busy ready status verify 11 figure 5. erase instruction timing a n a n ? 1 a 0 t cs t sv t hz t ew
cat93c76b www. onsemi.com 7 cs di standby 10 0 * * enable = 11 disable = 00 sk figure 6. ewen/ewds instruction timing sk cs di do standby high ? z high ? z 10 1 busy ready status verify 00 figure 7. eral instruction timing t cs t hz t sv t ew status verify sk cs di do standby high ? z 10 1 busy ready 0 0 figure 8. wral instruction timing d n d 0 t csmin t sv t hz t ew
cat93c76b www. onsemi.com 8 ordering information device order number specific device marking package type temperature range lead finish shipping cat93c76bli ? g 93c76d pdip ? 8 i = industrial ( ? 40 c to +85 c) nipdau tube, 50 units / tube cat93c76bvi ? gt3 93c76d soic ? 8, jedec i = industrial ( ? 40 c to +85 c) nipdau tape & reel, 3,000 units / reel cat93c76bvi ? g 93c76d soic ? 8, jedec i = industrial ( ? 40 c to +85 c) nipdau tube, 100 units / tube cat93c76bvi ? gt3l 93c76d soic ? 8, jedec i = industrial ( ? 20 c to +85 c) nipdau tape & reel, 3,000 units / reel cat93c76bve ? gt3 93c76d soic ? 8, jedec e = extended ( ? 40 c to +125 c) nipdau tape & reel, 3,000 units / reel cat93c76byi ? gt3 m76d tssop ? 8 i = industrial ( ? 40 c to +85 c) nipdau tape & reel, 3,000 units / reel cat93c76byi ? g m76d tssop ? 8 i = industrial ( ? 40 c to +85 c) nipdau tube, 100 units / tube cat93c76byi ? gt3l m76d tssop ? 8 i = industrial ( ? 20 c to +85 c) nipdau tape & reel, 3,000 units / reel cat93c76bye ? gt3 m76d tssop ? 8 e = extended ( ? 40 c to +125 c) nipdau tape & reel, 3,000 units / reel cat93c76bhu4i ? gt3 m3u udfn ? 8 i = industrial ( ? 40 c to +85 c) nipdau tape & reel, 3,000 units / reel cat93c76bzi ? gt3 m3ym msop ? 8 i = industrial ( ? 40 c to +85 c) nipdau tape & reel, 3,000 units / reel 8. all packages are rohs ? compliant (lead ? free, halogen ? free). 9. the standard lead finish is nipdau. 10. for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and ree l packaging specifications brochure, brd8011/d. 11. for additional package and temperature options, please contact your nearest on semiconductor sales office. 12. for detailed information and a breakdown of device nomenclature and numbering systems, please see the on semiconductor devic e nomenclature document, tnd310/d, available at www.onsemi.com
cat93c76b www. onsemi.com 9 package dimensions pdip ? 8, 300 mils case 646aa ? 01 issue a e1 d a l eb b2 a1 a2 e eb c top view side view end view pin # 1 identification notes: (1) all dimensions are in millimeters. (2) complies with jedec ms-001. symbol min nom max a a1 a2 b b2 c d e e1 l 0.38 2.92 0.36 6.10 1.14 0.20 9.02 2.54 bsc 3.30 5.33 4.95 0.56 7.11 1.78 0.36 10.16 eb 7.87 10.92 e 7.62 8.25 2.92 3.80 3.30 0.46 6.35 1.52 0.25 9.27 7.87
cat93c76b www. onsemi.com 10 package dimensions soic 8, 150 mils case 751bd ? 01 issue o e1 e a a1 h l c e b d pin # 1 identification top view side view end view notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec ms-012. symbol min nom max a a1 b c d e e1 e h 0o 8o 0.10 0.33 0.19 0.25 4.80 5.80 3.80 1.27 bsc 1.75 0.25 0.51 0.25 0.50 5.00 6.20 4.00 l 0.40 1.27 1.35
cat93c76b www. onsemi.com 11 package dimensions tssop8, 4.4x3 case 948al ? 01 issue o e1 e a2 a1 e b d c a top view side view end view 1 l1 l notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-153. symbol min nom max a a1 a2 b c d e e1 e l1 0o 8o l 0.05 0.80 0.19 0.09 0.50 2.90 6.30 4.30 0.65 bsc 1.00 ref 1.20 0.15 1.05 0.30 0.20 0.75 3.10 6.50 4.50 0.90 0.60 3.00 6.40 4.40
cat93c76b www. onsemi.com 12 package dimensions udfn8, 2x3 extended pad case 517az ? 01 issue o 0.065 ref copper exposed e2 d2 l e pin #1 index area pin #1 identification dap size 1.8 x 1.8 detail a d a1 b e a top view side view front view detail a bottom view a3 0.065 ref 0.0 - 0.05 a3 notes: (1) all dimensions are in millimeters. (2) refer jedec mo-236/mo-252. symbol min nom max a 0.45 0.50 0.55 a1 0.00 0.02 0.05 a3 0.127 ref b 0.20 0.25 0.30 d 1.95 2.00 2.05 d2 1.35 1.40 1.45 e 3.00 e2 1.25 1.30 1.35 e 2.95 0.50 ref 3.05 l 0.25 0.30 0.35 a
cat93c76b www. onsemi.com 13 package dimensions msop 8, 3x3 case 846ad ? 01 issue o e1 e a2 a1 e b d c a top view side view end view l1 l2 l detail a detail a notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-187. symbol min nom max a a1 a2 b c d e e1 e l 0o 6o l2 0.05 0.75 0.22 0.13 0.40 2.90 4.80 2.90 0.65 bsc 0.25 bsc 1.10 0.15 0.95 0.38 0.23 0.80 3.10 5.00 3.10 0.60 3.00 4.90 3.00 l1 0.95 ref 0.10 0.85
cat93c76b www. onsemi.com 14 on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 cat93c76b/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative ?

▲Up To Search▲

Price & Availability of CAT93C76BHU4I-GT3

	To Download CAT93C76BHU4I-GT3 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .